The present invention relates to electronics and more particularly to oscillators for generating clock signals.
RC (resistance-capacitance) oscillators are widely used in semiconductor products. This is because an RC oscillator is an inexpensive clock source and allows for the generation of various frequencies by changing resistance, capacitance, and/or reference voltage levels. For some conventional RC oscillator designs, an undesired offset voltage in the oscillator's voltage comparator will produce a clock signal having an unintended frequency.
FIG. 1A shows a conventional RC oscillator 100, which includes switches SW1 and SW2, a resistor R, a capacitor C, a comparator 102, three inverters 104, 106, and 110, and a D-type flip-flop (DFF) 108. FIG. 1B shows timing diagrams of a voltage Vcap across the capacitor C, an inverter output signal 107 (ϕ), and a clock signal clk_out of FIG. 1A, where the solid curves correspond to a no-offset situation in which a comparator reference voltage Vcmp is Vref/2 and there is no comparator offset voltage Voff, and the broken curves correspond to a positive comparator-offset situation in which effective Vcmp is (Vref/2+Voff).
As shown in FIG. 1B, at the beginning of operations, the voltage Vcap at the positive input to the comparator 102 is 0V. At that time, with the (positive) comparator reference voltage Vcmp applied to the negative-input port of the comparator 102, the comparator output 103 will be low, the output 105 (ϕ) of the inverter 104 will be high, the output 107 (ϕ) of the inverter 106 will be low, the Q output signal 109 of the DFF 108 (i.e., the clock signal clk_out) will be low, and the D input signal 111 of the DFF 108 (i.e., the output of the inverter 110) will be high.
With the inverter output 105 high and the inverter output 107 low, the switch SW1 will be closed and the switch SW2 will be open, such that the capacitor C will be charged by the high supply voltage Vref through the resistor R. As a result, the voltage Vcap rises from 0V towards Vref.
When the voltage Vcap surpasses the voltage Vcmp, the comparator output 103 will go high, the inverter output 105 will go low, and the inverter output 107 will go high. When the inverter output 107 (i.e., the clock input to the DFF 108) goes high, the DFF 108 will be clocked, thereby passing the high D input signal 111 to the Q output signal 109 and driving the clock signal clk_out high and the inverter output 111 low.
When the inverter output 105 goes low, the switch SW1 is opened, and, when the inverter output 107 goes high, the switch SW2 is closed. As a result, the capacitor C is rapidly discharged to ground through the switch SW2, and the voltage Vcap drops quickly to 0V. As a result, the comparator output 103 again goes low, the inverter output 105 again goes high, and the inverter output 107 again goes low. As a result, the switch SW1 is again closed and the switch SW2 is again opened, thereby again charging the capacitor C and driving the voltage Vcap towards Vref.
Here, too, when the voltage Vcap surpasses the voltage Vcmp, the comparator output 103 will go high, the inverter output 105 will go low, and the inverter output 107 will go high. When the inverter output 107 goes high, the DFF 108 will be clocked, thereby passing the low D input signal 111 to the Q output signal 109 and driving the clock signal clk_out low and the inverter output 111 high.
This alternating cycling continues with each successive charging cycle of the capacitor C generating the next half cycle of the clock signal clk_out. The duty cycle of the inverter output 107 (ϕ) is much less than 50%. The divide-by-two functionality of the DFF 108 is required to produce a clock signal clk_out with the desired 50% duty cycle.
When there is no comparator offset voltage Voff, the RC oscillator 100 will produce the clock signal clk_out at the desired frequency. If, however, there is a (positive or negative) comparator offset voltage Voff, then the frequency of the clock signal clk_out will differ from the desired frequency. In particular, if the comparator offset voltage Voff is positive, then the frequency of clk_out will be lower than the desired frequency, and, if the comparator offset voltage Voff is negative, then the frequency of clk_out will be higher than the desired frequency.
The time period T of the RC oscillator 100 of FIG. 1A is given by:
      T    =          rc      *              {                              2            *                          ln              ⁡                              (                2                )                                              +                      2            *                          ln              ⁡                              [                                  1                  +                                      Voff                    Vref                                                  ]                                                    }              ,where r is the resistance of the resistor R, and c is the capacitance of the capacitor C. When the comparator offset voltage Voff is 0V, then the time period T is 2rc*ln(2) or 1.386rc. When a positive comparator offset voltage Voff is 10% of the reference voltage Vref, then the time period T is 2rc*[ln(2)+ln(1.1)] or 1.577rc. Thus, a 10% positive comparator offset voltage results in a 14% increase in the time period T. When a negative comparator offset voltage Voff is 10% of the reference voltage Vref, then the time period T is 2rc*[ln(2)+ln(0.9)] or 1.176rc. Thus, a 10% negative comparator offset voltage results in a 15% decrease in the time period T.
The impact of a positive comparator offset voltage Voff is illustrated by the broken curves in FIG. 1B, which shows that it takes more time to drive the voltage Vcap to surpass the now-higher effective comparator reference voltage (Vcmp=Vref/2+Voff) during each charging cycle of the capacitor C, thereby lowering the frequency of clk_out below the desired frequency. Analogously, for a negative offset voltage Voff, it would take less time to drive the voltage Vcap to surpass the now-lower effective comparator reference voltage Vcmp during each charging cycle of the capacitor C, thereby raising the frequency of clk_out above the desired frequency.
It would be advantageous to have an RC oscillator that is less susceptible to comparator offset.